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 Post subject: Logic Analyser [ Monolith Pinout discovery ] Self Study
PostPosted: May 8th, 2022, 5:39 
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Joined: August 15th, 2006, 3:01
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Location: CDRLabs @ Chandigarh [ India ]
xHello,
To start with i know some of my friends will say hey how many times do you plan and have not done this ,Sorry guys this time its happening .Anyways the only logic analyser " Aka Analyzer " i have right now is Hantek LA5034 , I was working on a Monolith Card and microSD that i had posted here -> https://forum.hddguru.com/viewtopic.php?f=10&t=42369 , This was dead and after recovery i decided to interface the same to my card reader and checkout signals using my this logic analyser ,Result was negative , I used the Following adapter that rusolut had sent me without any prepayment " Thanks rusolut "

Attachment:
SolderingAdapterKit.jpg
SolderingAdapterKit.jpg [ 97.61 KiB | Viewed 7621 times ]


, Anyway i would like to ask my fellow friends out there which known pinout monolith and controller is best suited to start this kind of experiment .Also in this LA do we have to connect the ACLK logic analyser pin to some signal on monolith ,Or we have to set the trigger on a perticular NAND pin .GND is to be connected to the VSS of the Interface Right .

Attachment:
Snapshot_220508150601.jpg
Snapshot_220508150601.jpg [ 31.95 KiB | Viewed 7621 times ]

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Amarbir S Dhillon , Chandigarh Data Recovery Labs [India]
Logical,Semi Physical And Physical Data Recovery
Website-> http://www.chandigarhdatarecovery.com


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 Post subject: Re: Logic Analyser [ Monolith Pinout discovery ] Self Study
PostPosted: May 8th, 2022, 15:05 
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Joined: September 1st, 2018, 15:49
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Location: Poland
Nice of Rusolut that they decided to send you adapters for free.
When I asked about the possibility of PURCHASING adapters, I heard that they are not sold, but you need to undergo paid training.
Good for you.

It is best to start learning to look for pins with already known pinout and analysis of course of the already described signals.
How to do this says Jeremy in the video below:
https://www.youtube.com/watch?v=85SVNfA5Et0


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 Post subject: Re: Logic Analyser [ Monolith Pinout discovery ] Self Study
PostPosted: May 9th, 2022, 0:29 
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Joined: August 15th, 2006, 3:01
Posts: 3464
Location: CDRLabs @ Chandigarh [ India ]
Lukasz_W wrote:
Nice of Rusolut that they decided to send you adapters for free.
When I asked about the possibility of PURCHASING adapters, I heard that they are not sold, but you need to undergo paid training.
Good for you.

It is best to start learning to look for pins with already known pinout and analysis of course of the already described signals.
How to do this says Jeremy in the video below:
https://www.youtube.com/watch?v=85SVNfA5Et0


Hey ,
Nice to see you here brother ,Anyways they have stated to sell these too ,Check This section -> https://rusolut.com/visual-nand-reconst ... -adapters/ . They call it soldering adapter kit ,Well i have read documentation of monolith from Acelab and two articles from acelab blog , Rest i think i can start by analyzing known pinout .Any suggestions which pinout and controller is a bit easy

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Amarbir S Dhillon , Chandigarh Data Recovery Labs [India]
Logical,Semi Physical And Physical Data Recovery
Website-> http://www.chandigarhdatarecovery.com


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 Post subject: Re: Logic Analyser [ Monolith Pinout discovery ] Self Study
PostPosted: May 10th, 2022, 3:13 
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Joined: August 13th, 2016, 17:10
Posts: 193
Location: Vienna, Austria
Yes, GND is called VSS in the VLSI world. The name comes from Voltage and Source, whereas VDD comes from Voltage Drain, where Source and Drain are the pins of the transistors.


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 Post subject: Re: Logic Analyser [ Monolith Pinout discovery ] Self Study
PostPosted: May 10th, 2022, 4:19 
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Location: CDRLabs @ Chandigarh [ India ]
sourcerer wrote:
Yes, GND is called VSS in the VLSI world. The name comes from Voltage and Source, whereas VDD comes from Voltage Drain, where Source and Drain are the pins of the transistors.


Hi ,
Yes VSS is GND And VDD is +Ve Volts ,In My hantek LA5034 there are two channels ,Channel A and Channel B , Both have GND And CLK signals in a different pin ,After hooking all pins to required known signals of channel A to NAND i connect GND of channel one to VSS ,So far so good but were the hell to connect CLK ,How about CLE As this is the first one to change its state from 1 to 0 as far as acelab manual states ?

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Amarbir S Dhillon , Chandigarh Data Recovery Labs [India]
Logical,Semi Physical And Physical Data Recovery
Website-> http://www.chandigarhdatarecovery.com


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 Post subject: Re: Logic Analyser [ Monolith Pinout discovery ] Self Study
PostPosted: May 10th, 2022, 4:33 
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Joined: August 13th, 2016, 17:10
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Location: Vienna, Austria
I think the triggering depends on the amount of memory you have (in the logic analyzer and in the PC) and what/when exactly you want to measure. If you have enough memory, then I think you don't need a trigger, just record everything and analyze it afterwards. If you do not have enough memory or you intentionally just want to record a short period of time, you can define a trigger on one signal (or CLK), and then the Logic Analyzer will wait for the trigger to happen and then only fill the memory with 25% of the memory from the time directly before the trigger happened, and 75% of the memory dedicated to after the trigger happend. So you should use the trigger for signals that happen first (like CE - Chip-Enable Lines perhaps which should be active throughout the interesting communications).


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 Post subject: Re: Logic Analyser [ Monolith Pinout discovery ] Self Study
PostPosted: May 10th, 2022, 4:39 
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Joined: August 13th, 2016, 17:10
Posts: 193
Location: Vienna, Austria
From my point of view you dont have to connect ACLK for initially figuring out the pinout, but it might help later on to better synchronize the data if you want to use the LA for collecting data from the communication busses. I think it should help to get clean data from the data busses. Hmm, but the problem is that the data busses are a 2-way communication and you have 2 different clock pins for the 2 different directions, so I think you would have to choose which direction you are interested in. So I think it might be best if you would just not connect ACLK, so that you dont miss one of the directions.


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 Post subject: Re: Logic Analyser [ Monolith Pinout discovery ] Self Study
PostPosted: May 10th, 2022, 4:41 
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Joined: August 13th, 2016, 17:10
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Location: Vienna, Austria
I would suggest to connect the flash pins CLE, CLK, CE, ... to data pins of the LA.


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 Post subject: Re: Logic Analyser [ Monolith Pinout discovery ] Self Study
PostPosted: May 10th, 2022, 4:57 
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Joined: August 13th, 2016, 17:10
Posts: 193
Location: Vienna, Austria
I highly recommend the ONFI Gold standards to understand the Flash pinouts. The earlier versions are easier to understand the fundamentals, the latest version is recommended as a reference afterwards.


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 Post subject: Re: Logic Analyser [ Monolith Pinout discovery ] Self Study
PostPosted: May 10th, 2022, 6:40 
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Location: CDRLabs @ Chandigarh [ India ]
sourcerer wrote:
I would suggest to connect the flash pins CLE, CLK, CE, ... to data pins of the LA.


Hello,
There is No CLK Named Pin in NAND BTW

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Amarbir S Dhillon , Chandigarh Data Recovery Labs [India]
Logical,Semi Physical And Physical Data Recovery
Website-> http://www.chandigarhdatarecovery.com


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 Post subject: Re: Logic Analyser [ Monolith Pinout discovery ] Self Study
PostPosted: November 20th, 2022, 21:38 
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Joined: December 4th, 2012, 1:35
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Location: Adelaide, Australia
I would first, run the Hantek over with a fully loaded lorry. then buy a decent LA.


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