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Architecture of Silicon Motion controllers

September 12th, 2018, 10:01

Hi,
What are the architectures of Silicon Motion controllers?
using some product specifications and datasheets of Silicon Motion I saw that some uses 8051 and some '32bit RISC CPU'.
Do you know what is the architecture of the 32bit RISC CPU?
Do you know any other architectures that SM uses in their controllers?

Thanks.

Re: Architecture of Silicon Motion controllers

September 12th, 2018, 23:07

They have a lot of controllers. Have you already studied the older 8051 based and RISC ones, and looking for more research?
you can find many firmwares on the usual flashboot / usbdev sites and throw them in IDA, but unless you have a more specific purpose or focus, I think you will not get much help.
you might want to study the Phison work done a few years ago (badUSB IIRC) and see the general principals of reversing some usb controllers.

curious what your goal is on the research

Re: Architecture of Silicon Motion controllers

September 13th, 2018, 7:27

I tried to put some firmwares in IDA but I don't know which CPU disassembler to choose..
What are the most common cpu architectures for those controllers?
Do you know what is the architecture of Silicon Motion's 32bit RISC CPU?

Thanks.
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