why does WL SDR real block size follow a A.P (airthmatic progression while reading the pages?)

ie follows an​=a1​+(n−1)⋅d

where an is number of pages read. a1 = 2 and n is real block size and d is 3.

Where is it referred in ONFI standards? Can some one put some light here?

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Do you understand the addressing mode of the traditional SDR model? If you understand this concept, please provide an example. I will tell you the difference between the SDR mode and the WL SDR mode addressing. However, if you are not familiar with these concepts, I won't be able to help you get started.

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Auxiliary Tool Used For MonoLith Data Recovery, featuring the industry's most extensive Monolith pinouts
http://flash-matrix.com/

The beauty of not knowing is one can always know it at one point causally in the time domain. It would be still wonderful if you can share your knowledge base here for the ones who may know more than me (at the moment in time)?

And it is quite surprising that none of the other flash engineers not participating here. I still am very happy that you wrote atleast something here.

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PS: We never knew how to land on the south pole of moon either a few years ago. Just a reminder

This is not a knowledge point required for data recovery work (at least not at the current stage), so it is not necessary to understand it. However, if debugging, designing readers, and writing protocol decoding are required, then the foundational knowledge is necessary. Hynix and Toshiba NAND flash use the WL mode for addressing (read and program). Reads can be non-sequential, but programming must follow the prescribed rules.

_________________
Auxiliary Tool Used For MonoLith Data Recovery, featuring the industry's most extensive Monolith pinouts
http://flash-matrix.com/

Thanks for letting out the information. It's intriguing enough for me to explore and learn more.
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