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 Post subject: Support 6 byte page addressing ?
PostPosted: July 12th, 2023, 7:26 
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Does Rusolut plan to add support for memory chips with 6-byte addressing in the near future?
Micron/Intel memory with just such addressing will appear more and more often.


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 Post subject: Re: Support 6 byte page addressing ?
PostPosted: July 12th, 2023, 13:23 
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Joined: July 8th, 2019, 12:27
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The question chips currently exist in the Micron/Intel B3, N3, B4, N4 series, as well as in upcoming products awaiting release. These chips, in addition to using 6-byte addressing, have lower VCCQ levels and require DQS as a synchronization signal (cannot be downgraded to SDR mode through setting commands). They also have a new read retry process.

Among them, the ability to operate with a 1.2V VCCQ chip and support DQS cannot be achieved through software updates. Hardware modifications must be made accordingly. However, achieving this is urgent because in the future, almost all flash memory chips will adopt lower VCCQ voltages, similar to those of Micron/Intel chips. Toshiba SanDisk's latest chips still allow operation in SDR mode, but in the future, they may only support toggle mode, like Micron/Intel. Samsung's flash memory, which was released a long time ago, already only supports toggle mode.

Considering that adding an additional I/O for DQS signal may introduce implementation difficulties, a better solution is to reuse the RB2 signal for specific cases, acting as DQS. Normally, RB2 is only necessary when reading 2CH (1CE/2lun, 1CE/4lun) chips. Currently, these types of chips are usually used in SSDs rather than embedded devices like USB drives. In the future, as flash memory frequency increases, more and more devices won't require increasing channel count to improve data throughput. The RB2 pin may end up buried in the grave, just like 16-bit flash memory, in data recovery applications.

The 6-byte addressing mode is currently found only in Micron/Intel chips. I couldn't find any mention of 6-byte addressing in the latest ONFi 5.1 specification. Perhaps this is just a transitional phase or a specific implementation unique to Micron/Intel chips. Specifications and technical standards are often updated and adjusted based on industry demands and technological advancements, so there may be changes or updates in future versions.

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 Post subject: Re: Support 6 byte page addressing ?
PostPosted: December 12th, 2023, 8:24 
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Joined: September 23rd, 2019, 2:55
Posts: 60
Location: Poland
Is this new protocol "NVDDR3 3D NAND (6x ALE)" in VNR 8.0 is support 6 byte addressing?


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 Post subject: Re: Support 6 byte page addressing ?
PostPosted: December 13th, 2023, 2:32 
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Location: 中国大陆浙江省湖州市
6ALE=6-byte addressing, but I haven't tested it yet. Micron N38/N48/N58/B37/B47/B58/YMTC 3DV3/V4 requires the use of the 6ALE command rules. However, it seems that the VNR database does not have any of them, but it's okay, as VNR allows users to manually configure them

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