New NAND ID " 983E980376E4081E " With PS2251-19-26 CTRL

[fzabkar]

I don't understand why the conversation is now about sticking a potential divider on an output pin. @sourcerer was suggesting that we generate a 1.2V supply from a 1.8V source using such a divider. Clearly this is not appropriate, as simple electric circuit theory will easily demonstrate. Just plug in some resistor values, add a load, and watch the output voltage collapse.

On the other hand, if you want to modify your VNR hardware to accommodate 1.2V I/O levels, as @csava is suggesting, then add a bidirectional level translator.

[sin]

Hi there . You know what is even more interesting. One requires no such thing to read this particular chip. I could read mine well.
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[Amarbir[CDR-Labs]]

Hi there . You know what is even more interesting. One requires no such thing to read this particular chip. I could read mine well.
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Well,
I should not be having a issue with the adapter imho ,why because i am using a monolith adapter and i have soldered the TSOP48 to that adapter ,Rusoluts TS Cannot Make it Work ,If you can then you are Arvika Of NAND Recovery for India ,Why Not I Give You Access To My system And You Make This Work ,Also the NAND Config Csava suggested i have tried That doe not work ,I am able to see the chip Bitmap visually "But it makes no sense " . Rusolut Staff " Michal Gmurek " Says we will check it ,I mean they will check my Research they asked me to do .BTW the idea is to solve a case for the client not to argue and prove anything to anyone ,All of us a Good level engineers " Few Are Better then us Too No Doubt " . The Same Adapter i had used for the earlier case ,But As this Chip Has 2 NANDS ,I will Wire NAND #2 To Another adapter for a quick test ,If my conclusion is same ,I will dispatch this case to you ,You can check it and solve it and matter is buried and client is happy .

PS : I Am Fedup With VNR As a Tool As i am into providing Data To My clients And Not Involved into Research ,Since i have recharged Only 1 Case Is Solved .It Takes Months For Rusolut to solve my cases ,Infact Some are pending for More Then 1 Year Also Even After Providing Everything to Thier TS ,Including Arranging Of Donors and doing all the hard work for them so that they can solve the case ,This is the chip i am talking about in this - > http://www.flash-extractor.com/library/ ... C90535XBG/ .I hope Someone from Rusolut See This Post And Wake Up From Thier Slumber Sleep .

[sin]

Hello, let me know how it behaves now. Still you need to figure out a lot of geometry correctly. The chip would read well in general. Just make sure its not getting hot. If its getting hot then please suspend the operations immediately and figure out a way to calm out the chip (also possible).

Good luck and let me know also what support says in terms of the reading protocol as i just had the opportunity to set the protocol and not do any further geometry analysis at all(includes correct page size, block size, plane size and number of planes which byfar is 10mins-20mins job)...

Arvika is Arvika. Surely. But please do remember we(ISRO and Indians) have launched rockets far cheaper than what other nations have and Indian potential is rock solid

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[Amarbir[CDR-Labs]]

Hello, let me know how it behaves now. Still you need to figure out a lot of geometry correctly. The chip would read well in general. Just make sure its not getting hot. If its getting hot then please suspend the operations immediately and figure out a way to calm out the chip (also possible).

Good luck and let me know also what support says in terms of the reading protocol as i just had the opportunity to set the protocol and not do any further geometry analysis at all(includes correct page size, block size, plane size and number of planes which byfar is 10mins-20mins job)...

Arvika is Arvika. Surely. But please do remember we(ISRO and Indians) have launched rockets far cheaper than what other nations have and Indian potential is rock solid

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Well,
What we did is not correct ,Waiting For TS @ Rusolut To Figure out Something @ Coming Monday Till Next Friday

[Amarbir[CDR-Labs]]

@ Everyone ,
Is there a website were i can enter the NAND ID and it can tell me what is the NAND Model so that i can try searching for this datasheet

[sin]

[fzabkar]

This is the chip i am talking about in this - > http://www.flash-extractor.com/library/Other/TC90535XBG/

https://www.global.toshiba/content/dam/toshiba/migration/corp/techReviewAssets/tech/review/2011/high2011/high2011pdf/1103.pdf

https://i.blackhat.com/us-18/Wed-August-8/us-18-Valadon-Reversing-a-Japanese-Wireless-SD-Card-From-Zero-to-Code-Execution.pdf

https://core.ac.uk/download/pdf/223021902.pdf

During the internal inspection of the card and in images presented to the FCC, the device uses Toshiba TC58TFG7DDLAID flash memory in conjunction with a Toshiba 6PJ8XBG flash memory controller. The main chip on board the device is a TC90535XBG which includes a 32-bit RISC Media embedded Processor (MeP) running The Real-time Operating system Nucleus (TRON).

Attachments

Last edited by fzabkar on August 4th, 2023, 15:58, edited 2 times in total.

[sin]

Hello, let me know how it behaves now. Still you need to figure out a lot of geometry correctly. The chip would read well in general. Just make sure its not getting hot. If its getting hot then please suspend the operations immediately and figure out a way to calm out the chip (also possible).

Good luck and let me know also what support says in terms of the reading protocol as i just had the opportunity to set the protocol and not do any further geometry analysis at all(includes correct page size, block size, plane size and number of planes which byfar is 10mins-20mins job)...

Arvika is Arvika. Surely. But please do remember we(ISRO and Indians) have launched rockets far cheaper than what other nations have and Indian potential is rock solid

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Well,
What we did is not correct ,Waiting For TS @ Rusolut To Figure out Something @ Coming Monday Till Next Friday

Quite expected reply


Well, my aim was to help you realize that the chip reads well. EXACT settings to read and geometry is matter of your hardwork my friend.


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Attachments

[fzabkar]

Toshiba FlashAir:

https://fcc.report/FCC-ID/ZVZP42350FA2/1836372.pdf (internal photos)
https://fcc.report/FCC-ID/ZVZP42350FA2/1836373.pdf (manual)
https://fcc.report/FCC-ID/ZVZP42350FA2 (FCC documents)

[Amarbir[CDR-Labs]]

Hi Sin ,
No dont think thats the expected reply ,I have long age left that habit , Anyways i am still very convinced something is wrong somewhere seriously . This Includes you and me both our configs . I am sure next week i will have something from Rusolut TS , BTW Sin i saw this its just been added -> http://www.pc-3000flash.com/solbase/tas ... 3&lang=eng .I do have PC3K Flash But Not The Latest Update ,Which i Will Do Now . Also Frank Thanks a tonn for the research ,Thats another case i was referring to ,What i was saying is that if for example my NAND ID is 983E980376E4081E is there a website were i can feed this and it tells me what part number is it so that we could try and search for a datasheet of that nand to understand it better .i was waiting for csava comments on the subject of NAND config and reading .

BTW : Sin its time i restart my programming work ,GITHUB had some cool NAND PRojects and sourcecode to understand chips ,

[fzabkar]

The only web site I know of is ...

https://nand.gq/#/decode?pn=TC58TFG7DDLAID (from other Toshiba FlashAir SD card)
https://nand.gq/#/decode?pn=983E980376E4081E

... but no luck with your ID.

[fzabkar]

https://nand.gq/#/searchId?id=983E980376E4

Flash ID = 983E980376E4
Page Size = 16K
Blocks = 3324
Pages/Block = 1344
Part Number = TC58LJG9T24TA0D, TC58LJG9T25TA, TH58LKT0T25BA4C

https://nand.gq/#/decodeId?id=983E980376E4

[Amarbir[CDR-Labs]]

https://nand.gq/#/searchId?id=983E980376E4

Flash ID = 983E980376E4
Page Size = 16K
Blocks = 3324
Pages/Block = 1344
Part Number = TC58LJG9T24TA0D, TC58LJG9T25TA, TH58LKT0T25BA4C

https://nand.gq/#/decodeId?id=983E980376E4

Thanks ,
I will experiment at night and post results .Nice website i had seen this earlier long time ago also but not bookmarked

[Amarbir[CDR-Labs]]

The only web site I know of is ...

https://nand.gq/#/decode?pn=TC58TFG7DDLAID (from other Toshiba FlashAir SD card)
https://nand.gq/#/decode?pn=983E980376E4081E

... but no luck with your ID.

Boss ,
Earlier VNR Was using NAND ID's Like 983E980376 for this "983E980376E4081E " , Now they are using Like This "983E980376E4081E " , But industry is using like this 983E980376E4

[csava]

Reading a chip correctly is never a straightforward task. If you think that simply putting the chip into an adapter and pressing a button can achieve accurate reading, it may lead to a misunderstanding and create a communication barrier between us. The reason why most common chips can be easily read is due to the efforts made by the tool developers behind the scenes.

Take the example of the most common TSOP48 flash chip. Firstly, developers need to collect a large number of chips from different manufacturers and production periods and conduct tests and statistics on each one. These chips typically have the same data bus and fixed pin positions, but the locations of VCC/VCCQ/VSS/VSSQ might vary. So, it requires different power configurations to be arranged, allowing the tool to automatically switch to the correct configuration when you press the read button.

Secondly, the chip configuration data is often confidential and only accessible to authorized manufacturers. Even without the data sheet, one can try to guess a configuration based on correctly configured chips from the same manufacturer and different periods as a reference. The process involves reading and validating the chip step by step. This can be quite challenging for those without enough experience in this field, as it requires an understanding of the addressing method of NAND flash.

Thirdly, regarding Read Retry, in the era of 2D NAND flash, there was usually only one type of Read Retry. However, with the advent of 3D NAND, various methods to correct chip errors were introduced, including but not limited to Read Calibration, Read Offset, and ZQ Calibration. There are no publicly available instructions on the internet that tell us how to correctly configure the register commands and addresses, so almost all the work is done through reverse engineering.

Lastly, setting the correct voltage and thresholds is another complexity. While 2D NAND usually only requires 3.3VCC for reading, newer flash chips come with multiple voltage options, and you need to set different VCC and VCCQ accordingly.

I want to emphasize that even for the easiest-to-read non-Monolith chips, a significant amount of behind-the-scenes work is needed. Otherwise, you will be limited to using ready-made templates to solve previous old cases. If these templates have even a 1% difference from your case, you will get stuck at those differences. Every year, I encounter many cases abandoned by other laboratories because they couldn't recover the data. Typically, they get stuck in 1-2 places. As long as these issues are resolved, the case can be successfully recovered.

[sin]

Reading a chip correctly is never a straightforward task. If you think that simply putting the chip into an adapter and pressing a button can achieve accurate reading, it may lead to a misunderstanding and create a communication barrier between us. The reason why most common chips can be easily read is due to the efforts made by the tool developers behind the scenes.

Take the example of the most common TSOP48 flash chip. Firstly, developers need to collect a large number of chips from different manufacturers and production periods and conduct tests and statistics on each one. These chips typically have the same data bus and fixed pin positions, but the locations of VCC/VCCQ/VSS/VSSQ might vary. So, it requires different power configurations to be arranged, allowing the tool to automatically switch to the correct configuration when you press the read button.

Secondly, the chip configuration data is often confidential and only accessible to authorized manufacturers. Even without the data sheet, one can try to guess a configuration based on correctly configured chips from the same manufacturer and different periods as a reference. The process involves reading and validating the chip step by step. This can be quite challenging for those without enough experience in this field, as it requires an understanding of the addressing method of NAND flash.

Thirdly, regarding Read Retry, in the era of 2D NAND flash, there was usually only one type of Read Retry. However, with the advent of 3D NAND, various methods to correct chip errors were introduced, including but not limited to Read Calibration, Read Offset, and ZQ Calibration. There are no publicly available instructions on the internet that tell us how to correctly configure the register commands and addresses, so almost all the work is done through reverse engineering.

Lastly, setting the correct voltage and thresholds is another complexity. While 2D NAND usually only requires 3.3VCC for reading, newer flash chips come with multiple voltage options, and you need to set different VCC and VCCQ accordingly.

I want to emphasize that even for the easiest-to-read non-Monolith chips, a significant amount of behind-the-scenes work is needed. Otherwise, you will be limited to using ready-made templates to solve previous old cases. If these templates have even a 1% difference from your case, you will get stuck at those differences. Every year, I encounter many cases abandoned by other laboratories because they couldn't recover the data. Typically, they get stuck in 1-2 places. As long as these issues are resolved, the case can be successfully recovered.

Absolutely. You can clearly see in the bitmap. The whole geometry analysis is pending.The reading protocol some what worked....Lot to set with the voltages , sizes and reading protocol. One size never fits all and going off by even 1% would yield very unforgiving results.


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[Amarbir[CDR-Labs]]

Reading a chip correctly is never a straightforward task. If you think that simply putting the chip into an adapter and pressing a button can achieve accurate reading, it may lead to a misunderstanding and create a communication barrier between us. The reason why most common chips can be easily read is due to the efforts made by the tool developers behind the scenes.

Take the example of the most common TSOP48 flash chip. Firstly, developers need to collect a large number of chips from different manufacturers and production periods and conduct tests and statistics on each one. These chips typically have the same data bus and fixed pin positions, but the locations of VCC/VCCQ/VSS/VSSQ might vary. So, it requires different power configurations to be arranged, allowing the tool to automatically switch to the correct configuration when you press the read button.

Secondly, the chip configuration data is often confidential and only accessible to authorized manufacturers. Even without the data sheet, one can try to guess a configuration based on correctly configured chips from the same manufacturer and different periods as a reference. The process involves reading and validating the chip step by step. This can be quite challenging for those without enough experience in this field, as it requires an understanding of the addressing method of NAND flash.

Thirdly, regarding Read Retry, in the era of 2D NAND flash, there was usually only one type of Read Retry. However, with the advent of 3D NAND, various methods to correct chip errors were introduced, including but not limited to Read Calibration, Read Offset, and ZQ Calibration. There are no publicly available instructions on the internet that tell us how to correctly configure the register commands and addresses, so almost all the work is done through reverse engineering.

Lastly, setting the correct voltage and thresholds is another complexity. While 2D NAND usually only requires 3.3VCC for reading, newer flash chips come with multiple voltage options, and you need to set different VCC and VCCQ accordingly.

I want to emphasize that even for the easiest-to-read non-Monolith chips, a significant amount of behind-the-scenes work is needed. Otherwise, you will be limited to using ready-made templates to solve previous old cases. If these templates have even a 1% difference from your case, you will get stuck at those differences. Every year, I encounter many cases abandoned by other laboratories because they couldn't recover the data. Typically, they get stuck in 1-2 places. As long as these issues are resolved, the case can be successfully recovered.

Absolutely. You can clearly see in the bitmap. The whole geometry analysis is pending.The reading protocol some what worked....Lot to set with the voltages , sizes and reading protocol. One size never fits all and going off by even 1% would yield very unforgiving results.


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Well,
i will use the geometry that fzabkar gave and if it does not work i have no time ,Let the TS work on it ,I am Not Doing R&D on every damn case i receive

[csava]

I checked the chip configuration provided by fzabkar, and it matches exactly with the configuration I provided earlier. The BICS4 NAND flash uses the WL command for read and write addressing (triple addressing). Therefore, the page size should be three times the actual size, and the block size should be the actual size divided by three.

Even if we both provided incorrect configurations, you should still see some content on the bitmap, rather than FF, 00, or strange striped patterns filling the image. If you encounter such phenomena, you should first check the pin power configuration rather than suspecting the accuracy of the chip configuration I provided.

[sin]

" Even if we both provided incorrect configurations, you should still see some content on the bitmap, rather than FF, 00, or strange striped patterns filling the image. If you encounter such phenomena, you should first check the pin power configuration rather than suspecting the accuracy of the chip configuration I provided.

"

Very close
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