April 10th, 2013, 6:37
to confirm the NAND array voltage on another board, as you have already suggested. If anyone has a datasheet for the SandForce controller, then that might also tell us whether 2.8V is OK.
April 10th, 2013, 6:38
arvika wrote:Some nands need 2.8V to read properly. I think hhddrec can desolder one chip and check ID in reader - maybe we can find in database something more about this nands.
April 10th, 2013, 6:45
BlackST wrote:In a nutshell all these stories end with this conclusion : when it is not an evident problem that cannot be classified as failure i.e. Fuses or alike, no low cost solution... (probably they invented the week because it's never always Sunday).
@OP , SSDs are extremely difficult to deal with, if you really want to give services in this field to customers, seriously consider investing in equipment and know how .
P.s. Up now, on more than 1000 case, only few were power related and the outcome was bad (damage went beyond to the flash chips), on all the other the SSD were more or less working and the problem was ELSEWHERE. Having other identical devices at hand also helps.
April 10th, 2013, 6:50
fzabkar wrote:I found numerous studies of multilayer ceramic capacitor (MLCC) failures at low voltages, eg ...
http://downloads.hindawi.com/journals/a ... 147949.pdf
They suggest that typical failure modes are short circuits or low resistance. Leakage currents of several uA are typical in the period prior to total failure.
ISTM that the OCZ design is vulnerable to problems arising from such failures. The high resistances in the feedback paths of the two OFA regulators mean that it doesn't take much leakage in either of the Cff capacitors (C18 and C8) before the output voltage drops significantly. HDDs, OTOH, generally have feedback resistances of the order of 100s of ohms.
In the Vio case, the current through R23 and R22 appears to be around 5uA. AFAICS it would only need around 1uA of leakage in C18 for Vio to fall from 3.3V to 2.8V. If this is indeed what has happened, then I wonder if this is a common problem. In fact I'm wondering whether the Vcore supply has been affected as well.
April 10th, 2013, 7:44
April 10th, 2013, 7:47
hhddrec wrote:I think measure here. What you think?
see picture
April 10th, 2013, 7:54
Randy wrote:hhddrec wrote:I think measure here. What you think?
see picture
Yes, check voltage on a VCC pin against a ground.
April 10th, 2013, 7:57
Randy wrote:fzabkar, i think that applied IC 3.3 LDO is too weak to hold such a big load, like a NAND array.
April 10th, 2013, 8:05
April 10th, 2013, 8:07
Randy wrote:I think, if were was an active reset state, then we would not have seen anything in boot log.
April 10th, 2013, 8:50
April 10th, 2013, 11:00
fzabkar wrote:Perhaps resoldering it might be worth a try?
Doomer wrote:Seems that healing firmware problem by measuring Vcc is not working
April 10th, 2013, 13:42
April 10th, 2013, 22:41
April 11th, 2013, 0:03
April 11th, 2013, 3:23
April 11th, 2013, 14:44
hhddrec wrote:Wellcome GreenWD,
all post here are good welcome.
Including critical posts,
Thanks GreenWD
April 11th, 2013, 20:23
RCPch SAK0
Failed to read EPA=20038060, using ByteLaneMask=2, ByteLaneTable[0]=1
Failed to read EPA=20038060, using ByteLaneMask=1, ByteLaneTable[1]=0
Failed to read EPA=20038060, using ByteLaneMask=4, ByteLaneTable[2]=2
RCPch SHI
sysclk 150 MHz Hello,
@Kollis: How did you get clean output from that drive? I managed to get the output with rubbish:
CLI> PINRST
*** ROM 106 Mar 12 2009 20:29:35 ***
FW_SRC 0 SHA PASS!
*** EEPROM 207 Jan 3 2011 18:36:27 BuildServer:FW_Common_Critical_Fixes:P1_EEPROM_2_0_7_drop-290232 ***
IMFT45 Timing EPch
*** Patch 1.4.1 Mar 10 2011 16:23:47 BuildServer:P1_3_6_0_MP4_7:P1_3_6_0_MP4_7-300475 ***
IMFT45 Timing EPch
RCPch SAK0
ÿÿÿÿÿ\_ýÞýÞýÞø^(_ýÞýÞýÞm—ŒýÞÿÿÿÿìcýÞýÞýÞýÞýÞýÞÂvÄ1ýÞUdP‡
ýÞýÞýÞÿÿÿÕýÞýÞÕýÞýÞ .... and so on.
I'm using following COM settings:
Baud rate: 115200
Data bits: 8
Stop bits: 1
Parity, Flow control: None
As far as I know this can not be deducted, where encryption is used, I advise you to read the specification of the chip. And get a clean log into the terminal is simple: to close contacts 2-3 on ATMLH008, but what to do next has not yet been found. If there is any information as possible to flash it in this state, please share.RCPch SAK0
GetRootRecord(): Failed to read Root FID=2, IBA=7!
Micron Timing EPch RCPch SAK0+Fmgr
*** ERROR REPORT ***
IMPWIRE: 00300000
[PART]
SCHE: 80104404: 00000000
SATA: 81001804: 00000000
BUFR: 82201404: 00000000
FLSH; 83004004: 00000000
SIDX: 84400004: 00000000
PANIC: file=src/root/DirectRdWr.c line=197
PANIC: error=0x80120003 Flash Command received an interrupt
[BOOT MAIN] Root Not Found!
FW_SRC 0 SHA PASS!
*** EEPROM 207 Jan 3 2011 18:36:43 BuildServer:FW_Common_Critical_Fixes:P1_EEPROM_2_0 _7_drop-290232 ***
EPch SHI
sysclk 150 MHz
JTAG En 0
Link ...
upseems DR companies arent needed or wanted...This type of info is not available for public distribution. If the drive is no longer detected the only recourse is a RMA and get the drive replaced. If the drive was opened this is no longer an option though.
Found my dead OCZ SSD drive again and connected it to the serial port of my Ubuntu desktop.
This is what I get upon startup when i connect to it at 115200 Baud
RCPch SAK0+Fmgr
*** ERROR REPORT ***
IMPWIRE: 00300000
[PART]
SCHE: 80104404: 00000000
SATA: 81001804: 00000000
BUFR: 82201404: 00000000
FLSH; 83004004: 00000000
SIDX: 84400004: 00000000
PANIC: file=src/root/DirectRdWr.c line=197
PANIC: error=0x80120003 Flash Command received an interrupt
[BOOT MAIN] Root Not Found!
FW_SRC 0 SHA PASS!
*** EEPROM 207 Jan 3 2011 18:36:43 BuildServer:FW_Common_Critical_Fixes:P1_EEPROM_2_0_7_drop-290232 ***
EPch SHI
sysclk 150 MHz
JTAG En 0
Link ...
April 11th, 2013, 22:47
HaQue wrote:Hope that helps in some small way.HaQue
April 11th, 2013, 23:32
And get a clean log into the terminal is simple: to close contacts 2-3 on ATMLH008
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