What happens when the reserved blocks run out?

[ontariotech]

On flash memory, what happens when the reserved blocks (to cover substitute for bad blocks) run out?

[HaQue]

Interesting question.

I would say that different manufacturers would handle it differently. The spectrum would be from simply crashing as they haven't catered for it, to setting aside more blocks from user blocks.

has any work been done to disassemble controller firmware? I have been contemplating this for a while but haven't had the time. I was thinking that as we need to know XOR blocks and algos for the controllers, are these possible to ascertain from the firmware commonly shared around with the MP tools. I guess we would need to know what the controllers, ahh, cpu instruction set is and be able to reverse it like any other firmware. I may be talking out my ass here and have an unrealistic view...

Then we could see how they handle bad block depletion. Have you looked at any controller or NAND datasheets to see if it is mentioned anywhere?

Also I found some interesting research papers on some aspects of flash memory, so you might be able to hit on something with some google fu.

Cheers, let us know if you find out anything!

[HaQue]

If you read a datasheet of a nand chip it should explain it better than I can.

for example, a certain Micron chip has a page size of 4313 bytes. 4096(4k) bytes plus a spare area of 218 bytes. In a block there is 128 pages. so times the 4k + 218 by 128 = 5122K + 27K. a plane has 2,048 blocks and one device has 2 planes (the math is the same on these 2 as well).

So as you can see quite a lot of spare are exists.

many devices have different sizes of both page and spare area. This device example has it like this:

|4096|218|

but there are some where the spare area is evenly spaced inside the pages, or at the head (header) the tail as in this example or even with a number of different organisations on the device.

I am no expert on this stuff, this is my interpretation of it - I welcome improvements, ignore flames! .

As I said, grab a datasheet for a chip and it will be alot clearer.

Cheers,

HaQue

[Vulcan]

I welcome improvements

FYI you're not describing the reserved (or spare) blocks mentioned by the OP - you're describing the "spare bytes area" (sometimes called the out-of-band [OOB] area) which is included in each page. Although it's called the "spare bytes area", it is used (to a lesser or greater extent) by every flash controller I've encountered...

[HaQue]

Hmm, well yes I did answer the totally wrong question, thanks for pointing that out. What I described is not related to the OPs question at all, and re-reading the question, and also having a look at a datasheet, What I should have said was to look at the "error management" section of the datasheet. a small excerpt which I hope does not break the NDA is below from a micron datasheet. am guessing similar management exists in most NANDs.

Micron NAND devices are specified to have a minimum of 2,008 (NVB) valid blocks out
of every 2,048 total available blocks. This means the devices may have blocks that are
invalid when they are shipped. An invalid block is one that contains one or more bad
bits. Additional bad blocks may develop with use. However, the total number of available
blocks will not fall below NVB during the endurance life of the product.

Now a bit further into this section, Micron make some recommendations:

Always check status after a WRITE, ERASE, or DATA MOVE operation.
• Use some type of error detection and correction algorithm to recover from single-bit
errors.
• Use a bad-block replacement algorithm.

This last bullet point would imply that it is up to the manufacturer implementing the NAND to manage the bad blocks, so to get an answer to the OPs question, my first post on the subject would stand as my opinion - it would be a controller based solution, not a NAND chip based one.

Thanks for getting me to pay attention to finer details of questions, and to have a closer look at datasheets.

It facintes me the complexity involved in flash memory when on the surface the controller/nand/pcb looks like such a basic and simple device!

[HaQue]

Some more on this. I was researching something else and came across this page : http://www.openssd-project.org/wiki/Jasmine_FAQs

a few point stuck out to be relevant to your question:

The TutorialFTL is a sample FTL developed by Indilinx to demonstrate the basic skeleton of FTL for the Jasmine board. The TutorialFTL has several restrictions: 1. It is a page-mapping FTL, but no garbage collection is performed. It simply stops working when there is no more free blocks.

and

The GreedyFTL is another sample FTL developed by Sang-Pil Lim from VLDB Laboratory at Sungkyunkwan University under the guidance of Prof. Sang-Won Lee. The GreedyFTL is also a page-mapping FTL, but performs garbage collection if it runs out of free blocks. The victim block is chosen based on the greedy policy, i.e., the block which has the largest number of obsolete pages is selected as a victim during garbage collection.

FTL Flash Transition Layer (a reference at http://www-users.cs.umn.edu/~park/docs/sigmetrics10.pdf)

The flash translation layer (FTL) is a software/hardware in-
terface inside NAND flash memory. Since FTL has a critical
impact on the performance of NAND flash-based devices, a
variety of FTL schemes have been proposed to improve their
performance.

I have been searching for any reference to an example of a FTL that is relevant, meaning some docs or sourcecode of any FTL that may be used in a USB falash disk from the last 3 years or so. Does anyone have anything or any links, pointers.. apart from "you are wasting your time!"
cheers
HaQue

[ontariotech]

Thanks guys for all that info and links!