Newbie question on SSD translator tables

[RS96]

I’m a newbie and trying to understand some fundamentals of SSDs. Hoping someone can answer a few questions:

1. How large are translator tables (physical to logical) on SSDs. Obviously it’s dependent on the drive, but are these things large enough to take up multiple blocks, or can one sit in a single block?
2. Assuming they take up multiple blocks, how are they wear leveled in flash? Are they spread randomly / striped across different pages on different flash chips like normal user data, or is there a dedicated area in a single flash chip for storage once power is off?
3. If a translator table is spread across many different physical pages, how is this kept track of? Is there another table which keeps track of this distribution in order to reconstruct the table when it is needed?

Thanks

[sourcerer]

Translator Tables most likely take up about 70% of the RAM capacity of the drive. (The RAM capacity is usually determined after the translator table size)
For SSDs I assume that all SSDs have larger translator tables than what fits into a single page.
Yes, the translator tables are usually wear-leveled as well.
Some SSDs likely use higher-grade NAND flash (e.g. SLC ) for the translator tables. But I guess that most SSDs just have one single kind of NAND flash area.
Since you are new to SSDs, I would recommend my research paper on them:
http://www2.futureware.at/~philipp/ssd/ ... Manual.pdf
And you are most likely interested in scientific papers on "Flash Translation Layer".

[fzabkar]

Some SSDs likely use higher-grade NAND flash (e.g. SLC ) for the translator tables. But I guess that most SSDs just have one single kind of NAND flash area.

Maybe they redefine these FTL regions as pseudo-SLC?

[RS96]

Yes, the translator tables are usually wear-leveled as well..

Would this mean that the information required to build the translator tables in RAM is likely spread across each of the NAND chips (generally)? If that is the case, if a single chip dies and is unreadable or physically broken, does that mean that there is no access to all data on the SSD, or will the controller still be able to reconstruct usable translator tables? Assuming that this data is persisted only on the NAND chips and not the controller itself.

Busy reading through your paper now, thank you! Lots of information to try and process.

[Agrail]

Translation tables are written in pSLC format and occupy several blocks. As a rule, there is no specific area for storing service data. During the operation of the drive, the translation tables, as well as user data, are moved to less worn out areas. The size of the translator, excluding copies and previous versions, is approximately 1/1000 of the SSD capacity. And yes there are tables that index translation tables. And even tables that index tables that index translation tables. I have seen up to 5 such nesting levels.

[sourcerer]

Some SSDs likely use higher-grade NAND flash (e.g. SLC ) for the translator tables. But I guess that most SSDs just have one single kind of NAND flash area.

Maybe they redefine these FTL regions as pseudo-SLC?

Yes, exactly, pseudo-SLC. They can use a part of the flash as SLC. I haven't figured out how that is done in practice exactly, though. If anyone has any details about that, I would be interested.

[fzabkar]

This tech note briefly discusses pseudo-SLC:

https://business.kioxia.com/content/dam/kioxia/ncsa/en-us/business/memory/asset/KIOXIA_pSLC_for_IoT_devices_Tech_Brief.pdf