SSD drives is it worth to use in everyday life ?

[fzabkar]

I don't want really to try to waste my time and try to prove you wrong, I know that modern SSDs do that, because I RE them and I've seen it, that's enough for me.

Well it's not good enough for me, nor should it be good enough for anyone else. You have made an extremely contentious claim without any independent references.

In fact here's a research paper alluded to earlier by HaQue:
http://users.ece.cmu.edu/~omutlu/pub/fl ... date12.pdf

It is dated December 2012. The researches are testing the raw bit error rates (without ECC) of a "2-bit MLC NAND flash device manufactured in 3x-nm technology". The device is specified to survive 3000P/E cycles with 10-year data retention using ECC of 4-bits per 512 bits.

Read errors were tested "by continuously reading a given block". The researches state that a read error "happens when the data stored in a cell changes as a neighbouring cell on the same string is read over and over", so clearly they were testing for read disturb errors.

The bit error rates are shown in Fig 4. After 1000 cycles the read BER is around 10^-7. After 100K cycles the BER is approximately 10^-6.

If your "RE" is telling you a different story, then I'm sure the NAND manufacturers would very much like to hear from you.

[Doomer]

I don't want really to try to waste my time and try to prove you wrong, I know that modern SSDs do that, because I RE them and I've seen it, that's enough for me.

Well it's not good enough for me, nor should it be good enough for anyone else. You have made an extremely contentious claim without any independent references.

good thing about being me is that I don't want to save the world or fight the windmills
If it's not good enough for you then you can do your own RE, if you have brains to do it, of course.

In fact here's a research paper alluded to earlier by HaQue:
http://users.ece.cmu.edu/~omutlu/pub/fl ... date12.pdf

It is dated December 2012. The researches are testing the raw bit error rates (without ECC) of a "2-bit MLC NAND flash device manufactured in 3x-nm technology". The device is specified to survive 3000P/E cycles with 10-year data retention using ECC of 4-bits per 512 bits.

So you found a paper dated 2012 that researches technology dated 2009 and you want to impress me with it, well, I'm not impressed

If your "RE" is telling you a different story, then I'm sure the NAND manufacturers would very much like to hear from you.

I'm not having midlife crisis and not seeking public acceptance that desperately as some members of this forum
If you don't like what I'm telling you, you may scroll down my posts

[Keatah]

What's this "new tech" that I hear about? It's something that heats up the NAND cell, or a group of NAND cells, to something like thousands of degrees for an instant. When this is done they say it "resets" the cell to brand new. And with this built-in "heat treatment" prototypes are getting millions on top of millions of read/write/erase cycles.

http://www.engadget.com/2012/12/03/macr ... burning-o/

And then there's this PhaseChange memory, which I know even less about.
http://www.engadget.com/2012/07/18/micr ... ge-memory/

[fzabkar]

In fact here's a research paper alluded to earlier by HaQue:
http://users.ece.cmu.edu/~omutlu/pub/fl ... date12.pdf

It is dated December 2012. The researches are testing the raw bit error rates (without ECC) of a "2-bit MLC NAND flash device manufactured in 3x-nm technology". The device is specified to survive 3000P/E cycles with 10-year data retention using ECC of 4-bits per 512 bits.

So you found a paper dated 2012 that researches technology dated 2009 and you want to impress me with it, well, I'm not impressed

Let's put this into perspective.

In 2009 flash technology was such that, even after 100 thousand P/E cycles, each bit in a flash device could be read one million times with the expectation that there would be only one error. Now 4 years later, we take a flash device fresh off the production line and we find that it sustains a read error after only 10 reads. That's a BER of 10%. Thereafter every read produces an error, so the BER is 90% after 100 reads, 99% after 1000 reads, and so on.

Don't you think the researchers would have discovered this new phenomenon for themselves, and wouldn't there be consternation all over the Internet? Or do you believe that only you and the manufacturers are aware of this dark and dirty secret?

[Doomer]

Don't you think the researchers would have discovered this new phenomenon for themselves, and wouldn't there be consternation all over the Internet? Or do you believe that only you and the manufacturers are aware of this dark and dirty secret?

Last Flash Summit had it and I bet this one will
Why take my word? Come to Santa Clara and see for yourself, I'll even buy you Foster's if you make it

[Doomer]

What's this "new tech" that I hear about? It's something that heats up the NAND cell, or a group of NAND cells, to something like thousands of degrees for an instant. When this is done they say it "resets" the cell to brand new. And with this built-in "heat treatment" prototypes are getting millions on top of millions of read/write/erase cycles.

That's sounds interesting, if it's not BS

[Keatah]

I can see it now. People cooking their SSD instead of the freezer trick..

[arvika]

@fzabkar - I appreciate your big knowledge, but in this topic you are wrong. New nand flashes is really piece of crap :/

I make recovery from flashes form 5-6 years. Old nands has usually about 100-1000 errors while reading. New one has MILIONS of errors while reading. We say it is "problem chip" but in fact it is internal damage of chip - IMHO reason are: very bad quality and many more complicated construction than in the older nands.

Last edited by arvika on July 27th, 2013, 3:58, edited 2 times in total.

[Keatah]

On any SSD based system I recommend I also reiterate and double "emphasize" some kind of backup solution.

[pcimage]

@fzabkar - I appreciate your big knowledge, but in this topic you are wrong. New nand flashes is really piece of crap :/

I make recovery from flashes form 5-6 years. Old nands has usually about 100-1000 errors while reading. New one has MILIONS of errors while reading. We say it is "problem chip" but in fact it is internal damage of chip - IMHO reason are: very bad quality and many more complicated construction than in the older nands.

Exactly so, in the "olden days" of flash recovery we rarely used ECC algorithms to correct errors, as the were hardly any.

Now it's an absolute must, as virtually every new type of NAND flash we have in has thousands if not millions of ECC errors.

As Arvika says "problem chips" are abundant now, that require many retries and various other techniques including temperature and voltage adjustment to get as good a read as possible, but often a decent read is impossible due to the poor quality and massive quantity of uncorrectable bit errors.

Having said that, it does seem only to be certain known modules that are a problem, other just as new parts are fine, they read and ECC correct just dandy.

[HaQue]

I think like everything in life TextBook != Real_Life.

My Pajero is supposed to get 12.5litres/100km on the highway and 14litres/100km in the city. I think it is more like 17/100

[fzabkar]

Last Flash Summit had it and I bet this one will
Why take my word? Come to Santa Clara and see for yourself, I'll even buy you Foster's if you make it

I would prefer to read a technical paper on this new phenomenon, but I can't find any.

In any case ISTM that we may not need to bother with "RE" or lab tests. Surely we can get useful error rate information from the drive's SMART data?

SandForce firmware actually reports the number of read errors in the Raw Read Error Rate, Soft Read Error Rate, ECC On-the-Fly Error Count, Uncorrectable Sector Count, and Soft ECC Correction Rate (UECC) attributes.

Kingston SF-2000 Based SSD SMART Attributes:
http://hddguardian.googlecode.com/svn/d ... etails.pdf

For example, the RRER attribute is defined as follows:

Code:

Normalized Equation: 10log10 [BitsRead / (ReadErrors + 1)]

SectorsRead = Number of sectors read
SectorsToBits = 512 * 8
BitsRead = SectorsRead * SectorsToBits

Normalized Value Range:
Best = 120 (0 or 1 errors in 10^12 bits)
Worst = 38

Raw Usage:
[3-0] : Number of sectors read this power cycle
[6-4] : Read errors (UECC+URAISE)


Otherwise, if what you say is correct, and if the error logs are reasonably clean, then AISI the controller would have to preempt read degradation by relocating a block after a predetermined number of reads. You could test for this by reading the user space several times from start to finish while monitoring the Wear Levelling attributes.

[Keatah]

Why not just build reliable memory cells in the first place instead of doing all these gymnastics with the controller?

[arvika]

Why not just build reliable memory cells in the first place instead of doing all these gymnastics with the controller?

It is very good question.

[fzabkar]

Why not just build reliable memory cells in the first place instead of doing all these gymnastics with the controller?

Spare a thought for the QC engineer.

An SSD with these latest chips has just come off the production line. He now needs to generate a bad block map. Normally you would write various test patterns to each block (eg all zeros, all ones, alternate ones and zeros) and then read them back numerous times, while looking for just one bad read. How does he decide whether a failure is due to a genuinely bad cell, or is inherent in the design?

More importantly, how do the chip manufacturers test these chips?

[fzabkar]

What's this "new tech" that I hear about? It's something that heats up the NAND cell, or a group of NAND cells, to something like thousands of degrees for an instant. When this is done they say it "resets" the cell to brand new. And with this built-in "heat treatment" prototypes are getting millions on top of millions of read/write/erase cycles.

That's sounds interesting, if it's not BS

Plenty of patents on the subject ...
http://www.google.com/search?tbo=p&tbm= ... nix&num=20

Here are just a few:
http://patentimages.storage.googleapis. ... 281478.pdf
http://patentimages.storage.googleapis. ... 327719.pdf
http://patentimages.storage.googleapis. ... 281481.pdf
http://patentimages.storage.googleapis. ... 8061A2.pdf

Here is one by Rambus dating back to 2010:
http://patentimages.storage.googleapis. ... 344475.pdf

Macronix appear to be hoping for 1 billion P/E cycles, but they say it will take several months to run their tests.

[fzabkar]

The following article states that consumer workloads are "internally" estimated by Samsung not to exceed 10GB/day for most users.

Samsung SSD 840 Series Product Story - 3-bit/cell MLC NAND Flash:
http://www.samsung.com/global/business/ ... Flash.html

The following article estimates the endurance of TLC NAND at around 1000 P/E cycles.

Samsung SSD 840: Testing the Endurance of TLC NAND:
http://www.anandtech.com/show/6459/sams ... f-tlc-nand

"No manufacturer has openly wanted to discuss the endurance of TLC, so the numbers we have seen before have been educated guesses. 1,000 - 1,500 P/E cycles is what I've heard for TLC NAND."

Most reviewers and product testers assume a write amplification figure of 3x for SSDs in consumer applications, but the following article appears to suggest that Intel's SSDs have a typical write amplification of less than 1.1x for client workloads. OTOH the results for AnandTech's (typical?) server workload suggests a figure of 10x in enterprise applications.

A Look at Enterprise Performance of Intel SSDs:
http://www.anandtech.com/show/5518/a-lo ... intel-ssds

The following review suggests that Kingston's SSD products use Intel and Toshiba NAND. However, the article also suggests that the perceived lower quality of Kingston SSDs may be due to the practice of buying NAND in wafers rather than in pre-packaged form.

Kingston SSDNow V300 (120GB & 240GB) Review:
http://www.anandtech.com/show/6733/king ... 300-review

"Buying NAND seems to have become a trend among SSD OEMs lately. If you go back a year, everyone was using pre-packaged NAND but now at least OCZ, ADATA, Kingston and Transcend are buying NAND in wafers. I believe there's currently so much price competition (especially between SandForce OEMs) in the consumer SSD industry that costs need to be cut wherever possible. Buying NAND in wafers is cheaper because there are no binning or packaging costs involved and you also get a ton of lower quality NAND. It's actually a rather small percentage of the NAND wafer that's suitable for SSDs and the lower quality NAND usually gets used in devices where endurance isn't as critical (USB flash sticks, lower-end smartphones/tablets)."

Samsung's marketing blurb has this to say:

"The NAND chips used in the 840 Series SSD are carefully sorted and selected from the highest quality wafers of 3-bit/cell NAND using sophisticated 'binning' algorithms. They are then tuned for better endurance and painstakingly tested at both the component and system level before they are deemed appropriate for use in an SSD. Some vendors conclude the validation process at the wafer-level rather than revalidating at the chip-level. Chips that do not pass this second-level validation at Samsung are reserved for secondary, non-SSD applications."

[Keatah]

It never ceases to amaze me how a PR departments continually take sub-optimal products and spin them to look like the end-all be-all.

I have no doubt that eventually we'll see QLC and FLC in a few years. This progression is good for density and cost-effectiveness. But durability and longevity?

Don't get me wrong, I like the magic and romance of solid state storage, it's the next best thing to Superman holographic crystals. One big way we can speed up SSD even more is to eliminate the SATA connection and somehow magically (without f*cking up the current infrastructure) put the memory right on the bus and increase parallelism. That.. and minimizing controller involvement.

Meantime, my recommendation for making the SSD the APP and OS drive still stands. Userdata should still be placed on magnetics for the foreseeable future.

[thatdellguy]

My philosophy on the SSD drive technology: Let the end users waste their money on inferior technology now so that the SSD companies can use it toward research and development. Then purchase some after its reliable and much cheaper thanks to all the testers hard earned money. Personally I'm waiting for HAMR technology to revolutionize the drive industry.

[Keatah]

I'd like to see HAMR too. But I'm beginning to feel it's almost vapourware.

In the meantime, why not build up the cache on existing HDD's. Most of them have somewhere between 8 and 64MB. Why not make it a 256MB or 1GB size and read more nearby adjacent tracks arbitrarily and independently of the OS when user/system demands permit such luxury.