Thanks for positive comments, finally our first project is on the finish line, though it took much longer to polish than we expected.
I hope we won't disappoint those who waiting and those who expect to find new features.
We'll try to keep resources/documentation/algorihtms of VNR in open formats as much as possible, to move NAND DR&DF on the next level.
When more brains involved in research process, everybody wins - there's no need to wait months/years for support of new devices and database grows up like a snowball.
P.S. ~2 years ago our team realized that some "weak" chips work better with lowered power, the reason is obvious "less power = less noise", plus some physic's effects.
So we added power adjustment to reader on hardware level (controlled through software chip settings). The voltage range limited to optimal by firmware to 1.6....4.0V (those who ever open
ONFI know that modern chips work in power range 1.8V-3.6V).
Some chips work OK on 1.8V (Hynix/Micron). Others hang when power is lower than 2.2V (Toshiba/Sandisk). Work better means less bit errors when dumping (so ECC can correct it).
Mobile NAND/LPDDR works on 1.8V, wanna burn it - apply 3.3V.
Here's concept proof, posted several months ago.Here's copy for those who not tired to read this post

01.07.2014:
"A modern NAND flash memory chips have serious problem associated with TLC architecture and low endurance limit. In case when the chip is read with standard 3.3V power there is a large number of bit errors appear in image (so-called "bad chips"). Very often these bits can not be corrected by ECC and user data remain damaged and unrecoverable.
The NAND Reader of Visual Nand Reconstructor supports discrete power control of NAND chip in range 1.8V .... 4.0V. When lowering power of core/IO of NAND chip step by step the internal noise of chip reduces. The result is significant reduction of bit errors. To estimate number of bit errors the Bitmap viewer is used. Bit errors look like contaminations (dots) on the area with the same bytes (columns). Here's software screenshots of the same data block that is read with the three different levels of power 3.3V, 2.3V and 1.8V.
The last image with 1.8V shows clear data with very little number of bit errors. These errors can be fixed by ECC. Data is recoverable.
Do you still freeze or burn NAND chips? Give it up, there's a solution!"

Thanks.