3-wire serial protocol between SoC and smooth controller.

[Kota]

Hi all. I am researching the Seagate ST500DM002. I'm interested in a three-wire serial protocol between SoC and smooth controller, as well as between smooth controller and preamp. The oscillogram for communication between the smooth controller and the preamp is similar to the protocol for the TDA5360 chip, the documentation for which is available on the Internet (https://pdf1.alldatasheetru.com/datashe ... A5360.html). The first 8 bits are the address, the second 8 bits are the data. However, on my hard drive there is no pause between address and data, and clk with data is disabled when ENable is disabled. I did not find detailed documentation for other preamplifiers. Also, sometimes there are pauses in clk, or it’s not a pause, but a stretching of clk (Figure 1). Between the SoC and the smooth controller, the data transfer protocol is the same, only the data packets there have a completely different content. The clk line packet contains 9+15 clock impulse. At the same time, a packet of 16 clock impulse in a row occurs on the clk line. I don't know how to interpret these packets. Have you studied this protocol or maybe you have some documents from this list http://users.on.net/~fzabkar/hdd/hdd_ics.txt ?

Attachments

Figure 3. 16 impulse on clk line between SoC and smooth controller

Figure 2. 9+15 impulse on clk line between SoC and smooth controller

Figure 1. The red line on top is the clk line between smooth controller and preamp.

[fzabkar]

The SMOOTH protocol is described in the datasheet for the L7250 controller.

http://pdf.datasheetcatalog.com/datasheet/SGSThomsonMicroelectronics/mXyuswx.pdf

[Kota]

Here I wrote some nonsense. The preamp connects to the SoC, not to the smooth controller.