Have any of you tried to figure out how BCH works in the latest Silicon Motion controllers used in latest Samsung MicroSD cards and others such as Sandisk SD ImageMate series, where the SA_ECC structure is 16_16 and is easily corrected with a 285 polynomial, while the data area does not work with any primitive polynomial and different bit rotation, inversion and ECC before XOR where the ECC length is e.g. 114B, 124B ? In the times when FE was still alive, Sergej claimed that ECC in these memories is not BCH, which I cannot agree with, there must be some trick or non-standard polynomial that was used to generate ECC, because if SA is standard BCH, why for Data should be used some other error correction algorithm?

ps. In VNR I do seach polynomial for Data ECC by degree 8,9,10,11,12,13,14,15,16 and I didn't have any hits

I left you a message on Skype

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Auxiliary Tool Used For MonoLith Data Recovery, featuring the industry's most extensive Monolith pinouts
http://flash-matrix.com/

OK, but I do not have skype Have you tried to solve this problem? I suspect that maybe the data is xored with a second additional key, btw. a very strange thing.

Some SMI controllers use ECC after swapping bit positions, but I'm not sure if this applies to Samsung MicroSD cards. In some embedded controllers, a linear feedback shift register algorithm with feedback mechanism is employed, but currently, there are no universal tools to help analyze such complex situations

_________________
Auxiliary Tool Used For MonoLith Data Recovery, featuring the industry's most extensive Monolith pinouts
http://flash-matrix.com/

Dont ever underestimate the F***ckery that Flash manufacturers get up to. It is entirely possible they would use different schemes for SA and Data areas.
SM have some pretty weird schemes, but I am sure if you could talk to the engineers, it would be a very clever way to solve some embedded hardware limitations.

VNR have bit swapping (Rotate) - all 8 bit variant. No is not LFSR - only Samsung uses this in it's controllers. I have Sandisk 453e9803 chip and structure is similar to MicroSD Samsung Pro (white, grey, blue) 1138_32_32 or 1148_32_32 where SA_ECC is 16_16 and BCH ECC works for SA.

I will also add that Samsung abandoned its controllers in favor of SM in new MicroSD, UFD USB. For some reason in monolith USB they use standard configuration BCH ECC but not in microSD.
In all this chip you can find unxored marker "SMI". I also attach what LFSR looks like and there is no such thing, as far as I know, SM has never used LFSR.

I agree with HaQue statement that in some SSD controllers, both BCH and LDPC encoding/decoding cores coexist. Although it is not explicitly shown in the official product descriptions, this is indeed happening. The primary role of the BCH encoding/decoding core in these controllers is for Die Sorting. The BCH algorithm, compared to the LDPC algorithm, is deterministic and can more accurately assess the error rate in Sorting blocks, swiftly identifying areas that are on the verge of failure. Generally, manufacturers capable of designing LDPC controllers likely have experience with BCH controllers as well, and the BCH encoding/decoding core usually occupies a smaller proportion of the chip area. Therefore, incorporating a BCH encoding/decoding unit in the controller design allows it to adapt to a broader range of applications

_________________
Auxiliary Tool Used For MonoLith Data Recovery, featuring the industry's most extensive Monolith pinouts
http://flash-matrix.com/

No, I don't think so. XOR capable of generating regular patterns is inevitably an LFSR, but not being able to see regular patterns in a bit map doesn't necessarily mean it's not an LFSR. It depends on the length of the seed function, the number of bits in the LFSR register, and the position of the tap bit. As long as the controller manufacturer is willing, they can add any secret sauce that can be easily implemented in conventional algorithms, thus producing unexpected effects

_________________
Auxiliary Tool Used For MonoLith Data Recovery, featuring the industry's most extensive Monolith pinouts
http://flash-matrix.com/

OK, I found on the web that we may be dealing with something called DuoECC and it is based on BCH codes. This is the first time I've heard of such a thing. Controllers for SD based on this are: SM2705EN, SM2707EN.

Although the controller can integrate two different error correction units, I believe it's a variant of BCH rather than LDPC. You can verify it through a simple test. If you write a LBA pattern to a target MicroSD card, such as a 64GB card, and then compress the dump after reading, you can observe the difference. Typically, dumps using the BCH error correction algorithm have a relatively low compression rate, while LDPC achieves a high compression rate

_________________
Auxiliary Tool Used For MonoLith Data Recovery, featuring the industry's most extensive Monolith pinouts
http://flash-matrix.com/