Power and Bit errors

[bos]

VNR book says:

The power adjustment is required for chips with a high number of bit errors. Lower power equals to lower noise and better data quality.

It does however not state which of the powers that should be adjusted. Is it Vcc or VccQ? Or both?

Does the speed (high, normal, low) affect the readings if there are lots of bit errors? I mean, would a low speed and Vcc = VccQ = 2.5V yield better results than High speed, Vcc = VccQ = 2.5V?

[Arch Stanton]

determines the voltage level of I/O ports VccQ (pins 34& 39) The VNR reader supports the following power levels: 1,6V; 1,8V; 2,0V; 2,3V; 2,5V; 2,7V; 3,0V; 3,3V; 3,6V; 4,0V. The power adjustment is required for chips with a high number of bit errors. Lower power equals to lower noise and better data quality.

[arvika]

It depends from chip ID and type. Different chips "like" different settings. You need test it on different voltage values, speed combined with RR. Save the result at database. Next case with same ID you will take settings from notes. It speed up the work.

[fzabkar]

determines the voltage level of I/O ports VccQ (pins 34& 39) The VNR reader supports the following power levels: 1,6V; 1,8V; 2,0V; 2,3V; 2,5V; 2,7V; 3,0V; 3,3V; 3,6V; 4,0V. The power adjustment is required for chips with a high number of bit errors. Lower power equals to lower noise and better data quality.

I would have thought that the NAND core (Vcc) would be the voltage to play with. Vccq is the I/O voltage. ???

[bos]

Correct. VccQ is IO.

From the ONFI specs:

2.11.1. I/O Power (VccQ) and I/O Ground (VssQ)
VccQ and Vcc may be distinct and unique voltages. VccQ shall be less than or equal to Vcc,
including during power-on ramp. The device shall support one of the following VccQ/Vcc
combinations: