April 4th, 2018, 7:11
April 4th, 2018, 11:47
Amarbir[CDR-Labs] wrote:Most of The Controllers Embed Thier Controller No in the NAND dumps ,So To Arrange Them In Order Its Necessary To check Them and Set The Order of The Dumps.
Amarbir[CDR-Labs] wrote:I have a SM2236 Right Now and i Will Post The Details Soon Incase Someone Does Not Know .I had Some of The Initial NAND Tools From Acelab but never ventured deep into flash ,Things Are Very Different Now Buddy .In My Case i Have a Chip With 4 Parts Each ,Hence 16 Parts In Total
April 4th, 2018, 12:36
NANDoff wrote:Well... Seems like I opened up a can of worms there..
My take on it is ..
@Amarbir : you asked "My question was Why Read U51 As Chip 1 And U50 As Chip 2"
At some point in time, a solution / model was created with the chips in order of U51,U50 and so on..
IF you want to use this pre made solution / model then you need to follow the chip order specified by its creator. The solution / model could contain dump order switches within it.
This is why Acelab introduced the "Try all options of the order of chips" function. when running a solution.
Alternatively if you are the solution creator , there is no hard and fast rule as to which chips you read in what order. But there are sensible trends to follow to make everyone's life easier, like lowest to highest.
------------
"Sir ,
Since how much time are you doing NAND Chipoff "
Since its evolution from EEPROM in the late 80`s.. and still learning new stuff every day
April 4th, 2018, 20:13
Amarbir[CDR-Labs] wrote:NANDoff wrote:Well... Seems like I opened up a can of worms there..
My take on it is ..
@Amarbir : you asked "My question was Why Read U51 As Chip 1 And U50 As Chip 2"
At some point in time, a solution / model was created with the chips in order of U51,U50 and so on..
IF you want to use this pre made solution / model then you need to follow the chip order specified by its creator. The solution / model could contain dump order switches within it.
This is why Acelab introduced the "Try all options of the order of chips" function. when running a solution.
Alternatively if you are the solution creator , there is no hard and fast rule as to which chips you read in what order. But there are sensible trends to follow to make everyone's life easier, like lowest to highest.
------------
"Sir ,
Since how much time are you doing NAND Chipoff "
Since its evolution from EEPROM in the late 80`s.. and still learning new stuff every day
Thank You Sir ,
In VNR NAND Order Makes No Sense As We Have The Concept Of LBN LPN Corrent Me if this is untrue .Good You Hear About your long experience
April 5th, 2018, 2:30
Amarbir[CDR-Labs] wrote:Thank You Sir ,
In VNR NAND Order Makes No Sense As We Have The Concept Of LBN LPN Corrent Me if this is untrue .Good You Hear About your long experience
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