August 3rd, 2023, 16:54
August 3rd, 2023, 18:32
August 3rd, 2023, 20:58
sin wrote:Hi there . You know what is even more interesting. One requires no such thing to read this particular chip. I could read mine well.
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August 4th, 2023, 11:47
August 4th, 2023, 14:11
sin wrote:Hello, let me know how it behaves now. Still you need to figure out a lot of geometry correctly. The chip would read well in general. Just make sure its not getting hot. If its getting hot then please suspend the operations immediately and figure out a way to calm out the chip (also possible).
Good luck and let me know also what support says in terms of the reading protocol as i just had the opportunity to set the protocol and not do any further geometry analysis at all(includes correct page size, block size, plane size and number of planes which byfar is 10mins-20mins job)...
Arvika is Arvika. Surely. But please do remember we(ISRO and Indians) have launched rockets far cheaper than what other nations have and Indian potential is rock solid
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August 4th, 2023, 14:15
August 4th, 2023, 15:27
August 4th, 2023, 15:56
Amarbir[CDR-Labs] wrote:This is the chip i am talking about in this - > http://www.flash-extractor.com/library/Other/TC90535XBG/
During the internal inspection of the card and in images presented to the FCC, the device uses Toshiba TC58TFG7DDLAID flash memory in conjunction with a Toshiba 6PJ8XBG flash memory controller. The main chip on board the device is a TC90535XBG which includes a 32-bit RISC Media embedded Processor (MeP) running The Real-time Operating system Nucleus (TRON).
August 4th, 2023, 15:57
Amarbir[CDR-Labs] wrote:sin wrote:Hello, let me know how it behaves now. Still you need to figure out a lot of geometry correctly. The chip would read well in general. Just make sure its not getting hot. If its getting hot then please suspend the operations immediately and figure out a way to calm out the chip (also possible).
Good luck and let me know also what support says in terms of the reading protocol as i just had the opportunity to set the protocol and not do any further geometry analysis at all(includes correct page size, block size, plane size and number of planes which byfar is 10mins-20mins job)...
Arvika is Arvika. Surely. But please do remember we(ISRO and Indians) have launched rockets far cheaper than what other nations have and Indian potential is rock solid
--
Well,
What we did is not correct ,Waiting For TS @ Rusolut To Figure out Something @ Coming Monday Till Next Friday
August 4th, 2023, 17:10
August 5th, 2023, 0:14
August 5th, 2023, 0:35
August 5th, 2023, 1:21
August 5th, 2023, 3:14
fzabkar wrote:https://nand.gq/#/searchId?id=983E980376E4
Flash ID = 983E980376E4
Page Size = 16K
Blocks = 3324
Pages/Block = 1344
Part Number = TC58LJG9T24TA0D, TC58LJG9T25TA, TH58LKT0T25BA4C
https://nand.gq/#/decodeId?id=983E980376E4
August 5th, 2023, 3:17
fzabkar wrote:The only web site I know of is ...
https://nand.gq/#/decode?pn=TC58TFG7DDLAID (from other Toshiba FlashAir SD card)
https://nand.gq/#/decode?pn=983E980376E4081E
... but no luck with your ID.
August 5th, 2023, 5:14
August 5th, 2023, 8:36
csava wrote:Reading a chip correctly is never a straightforward task. If you think that simply putting the chip into an adapter and pressing a button can achieve accurate reading, it may lead to a misunderstanding and create a communication barrier between us. The reason why most common chips can be easily read is due to the efforts made by the tool developers behind the scenes.
Take the example of the most common TSOP48 flash chip. Firstly, developers need to collect a large number of chips from different manufacturers and production periods and conduct tests and statistics on each one. These chips typically have the same data bus and fixed pin positions, but the locations of VCC/VCCQ/VSS/VSSQ might vary. So, it requires different power configurations to be arranged, allowing the tool to automatically switch to the correct configuration when you press the read button.
Secondly, the chip configuration data is often confidential and only accessible to authorized manufacturers. Even without the data sheet, one can try to guess a configuration based on correctly configured chips from the same manufacturer and different periods as a reference. The process involves reading and validating the chip step by step. This can be quite challenging for those without enough experience in this field, as it requires an understanding of the addressing method of NAND flash.
Thirdly, regarding Read Retry, in the era of 2D NAND flash, there was usually only one type of Read Retry. However, with the advent of 3D NAND, various methods to correct chip errors were introduced, including but not limited to Read Calibration, Read Offset, and ZQ Calibration. There are no publicly available instructions on the internet that tell us how to correctly configure the register commands and addresses, so almost all the work is done through reverse engineering.
Lastly, setting the correct voltage and thresholds is another complexity. While 2D NAND usually only requires 3.3VCC for reading, newer flash chips come with multiple voltage options, and you need to set different VCC and VCCQ accordingly.
I want to emphasize that even for the easiest-to-read non-Monolith chips, a significant amount of behind-the-scenes work is needed. Otherwise, you will be limited to using ready-made templates to solve previous old cases. If these templates have even a 1% difference from your case, you will get stuck at those differences. Every year, I encounter many cases abandoned by other laboratories because they couldn't recover the data. Typically, they get stuck in 1-2 places. As long as these issues are resolved, the case can be successfully recovered.
August 5th, 2023, 10:51
sin wrote:csava wrote:Reading a chip correctly is never a straightforward task. If you think that simply putting the chip into an adapter and pressing a button can achieve accurate reading, it may lead to a misunderstanding and create a communication barrier between us. The reason why most common chips can be easily read is due to the efforts made by the tool developers behind the scenes.
Take the example of the most common TSOP48 flash chip. Firstly, developers need to collect a large number of chips from different manufacturers and production periods and conduct tests and statistics on each one. These chips typically have the same data bus and fixed pin positions, but the locations of VCC/VCCQ/VSS/VSSQ might vary. So, it requires different power configurations to be arranged, allowing the tool to automatically switch to the correct configuration when you press the read button.
Secondly, the chip configuration data is often confidential and only accessible to authorized manufacturers. Even without the data sheet, one can try to guess a configuration based on correctly configured chips from the same manufacturer and different periods as a reference. The process involves reading and validating the chip step by step. This can be quite challenging for those without enough experience in this field, as it requires an understanding of the addressing method of NAND flash.
Thirdly, regarding Read Retry, in the era of 2D NAND flash, there was usually only one type of Read Retry. However, with the advent of 3D NAND, various methods to correct chip errors were introduced, including but not limited to Read Calibration, Read Offset, and ZQ Calibration. There are no publicly available instructions on the internet that tell us how to correctly configure the register commands and addresses, so almost all the work is done through reverse engineering.
Lastly, setting the correct voltage and thresholds is another complexity. While 2D NAND usually only requires 3.3VCC for reading, newer flash chips come with multiple voltage options, and you need to set different VCC and VCCQ accordingly.
I want to emphasize that even for the easiest-to-read non-Monolith chips, a significant amount of behind-the-scenes work is needed. Otherwise, you will be limited to using ready-made templates to solve previous old cases. If these templates have even a 1% difference from your case, you will get stuck at those differences. Every year, I encounter many cases abandoned by other laboratories because they couldn't recover the data. Typically, they get stuck in 1-2 places. As long as these issues are resolved, the case can be successfully recovered.
Absolutely. You can clearly see in the bitmap. The whole geometry analysis is pending.The reading protocol some what worked....Lot to set with the voltages , sizes and reading protocol. One size never fits all and going off by even 1% would yield very unforgiving results.
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August 5th, 2023, 11:25
August 5th, 2023, 11:38
"csava wrote:
" Even if we both provided incorrect configurations, you should still see some content on the bitmap, rather than FF, 00, or strange striped patterns filling the image. If you encounter such phenomena, you should first check the pin power configuration rather than suspecting the accuracy of the chip configuration I provided.
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