HDD GURU FORUMS

Hi Friends ,
Anyone Worked On This NAND ID Earlier ,Also Anyone Worked On PS2251-19-26 Controller In VNR With Results ,The PS2251-19 Details Are Here - > https://www.phison.com/en/solutions/con ... ovable/usb .This Is From a Kingston DataTraveler Exodia M With 64GB Capacity -> https://www.kingston.com/en/usb-flash-drives

Toshiba NAND : 983E980376E4081E

Friends ,
Sharing Some Images of The Circuit Board

The difficulty lies not only in correctly reading the chip, but reading the chip is the first step

csava wrote:The difficulty lies not only in correctly reading the chip, but reading the chip is the first step

Well,
Did Not Work ,Something Is Wrong Somewhere ,Testing Voltages Tommorow In Office

Applicable to your case.Check 1, 2, 23, 24, 25, 26, 47, 48; they may have slight variations across different cases

Hi ,
I have Measured The Pins ,I will post results when i reach Home .VCCQ is 1.2 Volts and The Rusolut Reader Does Not Support Less Then 1.6 Volts ,How Are We Able To Read such Chips Then .

Amarbir[CDR-Labs] wrote:Hi ,
I have Measured The Pins ,I will post results when i reach Home .VCCQ is 1.2 Volts and The Rusolut Reader Does Not Support Less Then 1.6 Volts ,How Are We Able To Read such Chips Then .

The chip can be read by VNR with VCC=3.3V and VCCQ=1.8V. I am using the adapter I designed, which aims to facilitate the replacement of voltage pins with special configurations. For the 3K, I have read the latest updates, and they have added this chip to the chip database. However, I haven't tested the software with this new addition yet. As for the FE, there were significant issues when reading low voltage chips with the existing hardware. But I have successfully addressed this problem by patch. You can find more information about it on my website.

csava wrote:

Amarbir[CDR-Labs] wrote:Hi ,
I have Measured The Pins ,I will post results when i reach Home .VCCQ is 1.2 Volts and The Rusolut Reader Does Not Support Less Then 1.6 Volts ,How Are We Able To Read such Chips Then .

The chip can be read by VNR with VCC=3.3V and VCCQ=1.8V. I am using the adapter I designed, which aims to facilitate the replacement of voltage pins with special configurations. For the 3K, I have read the latest updates, and they have added this chip to the chip database. However, I haven't tested the software with this new addition yet. As for the FE, there were significant issues when reading low voltage chips with the existing hardware. But I have successfully addressed this problem by patch. You can find more information about it on my website.

Hi,
The TS Team of rusolut had asked me to measure voltages when the NAND was removed on all pins of the PCB Also they had asked me to measure continuity of certain pins to specific pins

I had an idea for the VCCQ of 1.2 Volts: You could try to use a Voltage divider made out of 2 resistors. Adding just 2 resistors should be a relatively easy modification for the adapters I guess.

same chip id. Dump from a block . Page 01

Some decryption. Some Tables.
Good Night/Good Morning
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sourcerer wrote:I had an idea for the VCCQ of 1.2 Volts: You could try to use a Voltage divider made out of 2 resistors. Adding just 2 resistors should be a relatively easy modification for the adapters I guess.

You cannot use a potential divider as a power source. As soon as you draw power from the divider, the voltage drops. Instead, you can add a 1.2V LDO regulator for $1.

Hello. I would say one can if one knew what is the load current of the VCCQ line

__________Vin
|
|
r1
|
|------>load current to vccq and node voltage required.
r2
|
|
Gnd

However I would stick to 2x emitter followers. Why spend even a 1$

One should make sure that input current is always limited to a very low value and try not to fry the reader

PS
I could dexor my dump with same chip id. The controller is Innostor. I will give a shot with Exodia M series too...
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I think I am getting there

Loads to learn and explore. How would one go about "set features" || making custom file for RR || read sensitivity setting in VNR ?

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sin wrote:Hello. I would say one can if one knew what is the load current of the VCCQ line

__________Vin
|
|
r1
|
|------>load current to vccq and node voltage required.
r2
|
|
Gnd

However I would stick to 2x emitter followers. Why spend even a 1$

One should make sure that input current is always limited to a very low value and try not to fry the reader

PS
I could dexor my dump with same chip id. The controller is Innostor. I will give a shot with Exodia M series too...
--

I believe this is an ideal model, but it is not applicable in practical circuits. This is because you have not considered the internal resistances of the I/O pins. The I/O pins are controlled by two N-MOSFETs, and you need to take into account the gate impedance

Very good input. Its surely a very basic idea. However please correct me. Isn't VCCQ a constant DC signal. Why would you consider impedances in that case?
Putting LDO surely does not seems considerate towards impedance either.


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sin wrote:I think I am getting there

Loads to learn and explore. How would one go about "set features" || making custom file for RR || read sensitivity setting in VNR ?

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I've been searching for such an option all along, but unfortunately, I only found something similar in the software dialog box of the chip. However, that's not the option I'm looking for. I need the ability to customize the entry for commands, addresses, and data. It would be great if I could use a scripting language as well. I contacted VNR's technical support, but they haven't provided any response, and it seems like they are intentionally ignoring this issue

sin wrote:Very good input. Its surely a very basic idea. However please correct me. Isn't VCCQ a constant DC signal. Why would you consider impedances in that case?
Putting LDO surely does not seems considerate towards impedance either.


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When you integrate such a voltage divider system into the circuit, the internal resistance of the I/O pins and the pull-down resistor of the voltage divider are in series when the output is high. Therefore, when calculating the voltage at the midpoint, you also need to take the internal resistance of the pins into account. I believe this voltage divider system is not suitable for such an environment. A better approach would be to modify the gate threshold voltage of the internal N-MOSFETs in the I/O pins and provide the correct VCCQ bus voltage. This is the implementation principle of the Flash Extractor Reader Low Voltage Modification Patch that I have already completed. I apologize for any potential misunderstandings caused by my limited English proficiency while explaining this issue

Friends ,
I returned back this case and god is very mercyfull ,He gave me a HP 128GB with same controller + 2 NANDS instead of 1 ,Same Issue in Reading

csava wrote:

sin wrote:Very good input. Its surely a very basic idea. However please correct me. Isn't VCCQ a constant DC signal. Why would you consider impedances in that case?
Putting LDO surely does not seems considerate towards impedance either.


--

When you integrate such a voltage divider system into the circuit, the internal resistance of the I/O pins and the pull-down resistor of the voltage divider are in series when the output is high. Therefore, when calculating the voltage at the midpoint, you also need to take the internal resistance of the pins into account. I believe this voltage divider system is not suitable for such an environment. A better approach would be to modify the gate threshold voltage of the internal N-MOSFETs in the I/O pins and provide the correct VCCQ bus voltage. This is the implementation principle of the Flash Extractor Reader Low Voltage Modification Patch that I have already completed. I apologize for any potential misunderstandings caused by my limited English proficiency while explaining this issue

Sounds cool to me. What you are referring to is internal resistances.