A lot of my work is reverse engineering RR for Soft-Center/Sergey, so I’d like to think I’m a good source.
How Sergey chooses to implement this information is on him.
First, I don’t like calling them RR codes, the phrase has no meaning, I prefer “sensitivity registers”.
Modern NAND chips are broken into three pages (Lower, Middle Upper), even on NAND using a STD interface, not just WL. Let’s say you read a NAND chip and you see a band of uncorrectable errors (page address % 3) = 2 (middle) it probably has an incorrect RR value. If you modify the registers responsible for that band until you find “the sweet spot” you will get a range of values that give you a good read. If you run ECC combine over multiple reads using different registers in that range you’ll get a perfect image.
This method works on SK Hynix, Samsung and Toshiba/SanDisk NAND.
Lots of different factors that go into choosing a proper RR value besides setting register 0xB0 to 0x4F which is why RR is so poorly understood.
“Test Retry” – Registers can be initialized with KNOWN starting values that can get you in the correct range. FE calculates the best value based on the number of corrected errors.
“Test Retry Tune” – IMHO terrible solution, but I digress, this will take your Test Retry value and brute force the best register value by corrected errors. It’s slow, unoptimized, and doesn’t take into account any geometrical factors.
“Test Random” – Sends random data to the registers, like winning the lotto.
RR is actually pretty cool, it's not about taking damaged NAND and making it usable, more like finding taking good NAND and making it readable.
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